PN-2669M
- 3 -
ADJUSTMENT
Clock accuracy
adjustment
1. Set a universal timer to TP401(T-BASE), and adjust TC401 so that a reading of
the meter is 0+0.1/-0 sec./day.
Universal timer
EXPLANATION OF IC
051-6360-30
SAA7706H N20 Car radio Digital Signal Processor
Terminal Description
pin
1: VDACP
: positive reference voltage ADC1, ADC2,
ADC3 and level-ADC
pin
2: VDACN1
: ground reference voltage ADC1
pin
3: LEVEL
: LEVEL input pin; via this pin the level of the
FM signal or level of the AM signal is fed
to the DSP1; the level information is used in
the DSP1 for dynamic signal processing
pin
4: NAV_GND
: common mode reference input pin of the
navigation signal (pin AM_L/NAV)
pin
5: POM
: power-on mute of the QFSDAC; timing is
determined by an external capacitor
pin
6: RRV
: rear; right audio output of the QFSDAC
pin
7: AUX_L
: left channel of analog AUX input
pin
8: AUX_R
: right channel of analog AUX input
pin
9: RLV
: rear; left audio output of the QFSDAC
pin 10: VSS A2
: ground supply analog part of the QFSDAC
and SPDIF bitslicer
pin 11: VDD A2
: positive supply analog part of the QFSDAC
and SPDIF bitslicer
pin 12: VREFDA
: voltage reference of the analog part of QFS-
DAC
pin 13: FRV
: front; right audio output of the QFSDAC
pin 14: CD_R_GND
: common-mode reference input pin for analog
CD_R or TAPE_R in the event of separated
ground reference pins for left and right are
used
pin 15: DSP2_INOUT2 : flag input/output 2 of the DSP2-core (DSP2-
flag) I2C-bus configurable
pin 16: FLV
: front; left audio voltage output of the QFS-
DAC
pin 17: DSP2_INOUT1 : flag input/output 1 of the DSP2-core (DSP2-
flag) I2C-bus configurable
pin 18: DSP2_INOUT3 : flag input/output 3 of the DSP2-core (DSP2-
flag) I2C-bus configurable
pin 19: DSP2_INOUT4 : flag input/output 4 of the DSP2-core (DSP2-
flag) I2C-bus configurable
pin 20: LOOPO
: SYSCLK output (256fs)
pin 21: TP1
: for test purpose only; this pin may be left
open or connected to ground
pin 22: VDD D3V7
: positive supply (peripheral cells only)
pin 23: VSS D3V7
: ground supply (peripheral cells only)
pin 24: SPDIF2
: SPDIF input 2; can be selected instead of
SPDIF1 via I2C-bus bit
pin 25: SPDIF1
: SPDIF input 1; can be selected instead of
SPDIF2 via I2C-bus bit
pin 26: SYSFS
: system fs clock input
pin 27: CD_WS
: digital CD-source word select input; I2S-bus
or LSB-justified format
pin 28: CD_DATA
: digital CD-source left-right data input; I2S-
bus or LSB-justified format
pin 29: CD_CLK
: digital CD-source clock input I2S-bus or
LSB-justified format
pin 30: IIS_CLK
: clock output for external I2S-bus receiver; for
example headphone or subwoofer
pin 31: IIS_IN1
: data 1 input for external I2S-bus transmitter;
e.g. audio co-processor
pin 32: IIS_IN2
: data 2 input for external I2S-bus transmitter;
e.g. audio co-processor
pin 33: IIS_WS
: word select output for external I2S-bus re-
ceiver; for example headphone or subwoof-
er
pin 34: IIS_OUT1
: data 1 output for external I2S-bus receiver
or co-processor
pin 35: IIS_OUT2
: data 2 output for external I2S-bus receiver or
co-processor
pin 36: VDD D3V6
: positive supply (peripheral cells only)
pin 37: VSS D3V6
: ground supply (peripheral cells only)
pin 38: DSP1_IN1
: flag input 1 of the DSP1-core
pin 39: DSP1_IN2
: flag input 2 of the DSP1-core
pin 40: DSP1_OUT1
: flag output 1 of the DSP1-core
pin 41: DSP1_OUT2
: flag output 2 of the DSP1-core
pin 42: DSP_RESET
: general reset of chip (active LOW)
pin 43: RTCB
: asynchronous reset test control block; con-
nect to ground (internal pull-down)
pin 44: SHTCB
: shift clock test control block (internal pull-
down)
pin 45: TSCAN
: scan control active high (internal pull-down)
pin 46: VDD D3V5
: positive supply (peripheral cells only)
pin 47: VSS D3V5
: ground supply (peripheral cells only)
pin 48: VDD D3V1
: positive supply (core only)
pin 49: VSS D3V1
: ground supply (core only)
pin 50: VSS D3V2
: ground supply (core only)
pin 51: VDD D3V2
: positive supply (core only)
pin 52: VDD D3V3
: positive supply (core only)
pin 53: VSS D3V3
: ground supply (core only)
pin 54: VSS D3V4
: ground supply (core only)
pin 55: VDD D3V4
: positive supply (core only)
pin 56: A0
: slave sub-address I2C-bus selection or seri-
al data input test control block
pin 57: SCL
: serial clock input I2C-bus
pin 58: SDA
: serial data input/output I2C-bus
pin 59: RDS_CLOCK
: radio data system bit clock output or RDS
external clock input I2C-bus bit controlled
pin 60: RDS_DATA
: radio data system data output
pin 61: SEL_FR
: AD input selection switch to enable high
ohmic FM_MPX input at fast tuner search on
FM_RDS input
pin 62: VSS (OSC)
: ground supply (crystal oscillator only)
pin 63: OSC_IN
: crystal oscillator input
pin 64: OSC_OUT
: crystal oscillator output
pin 65: VDD (OSC)
: positive supply (crystal oscillator only)
pin 66: AM_FM R
: right channel AM/FM input; analog input pin
pin 67: AM_FM L
: left channel AM/FM input; analog input pin
pin 68: CD_R
: right channel of analog CD input
pin 69: CD_L
: left channel of analog CD input
pin 70: DVD_R
: right channel of analog DVD input
pin 71: PHONE
: common mode PHONE signal, analog input
pin
pin 72: DVD_L
: left channel of analog DVD input
pin 73: PHONE_GND
: common mode reference input pin of the
PHONE signal
pin 74: VDD A1
: positive supply analog (ADC1, ADC2, ADC3
and level-ADC only)
pin 75: VSS A1
: ground supply analog (ADC3 and level-ADC
only)
pin 76: VDACN2
: ground reference voltage (ADC2)
pin 77: DVD_GND
: common mode reference input pin for ana-
log DVD in the event of separated ground
reference pins used for DVD
pin 78: VREFAD
: common mode reference voltage ADC1,
ADC2, ADC3 and level-ADC
pin 79: FM_RDS
: FM RDS signal; analog input pin
pin 80: FM_MPX
: FM multiplex signal; analog input pin
Item
Procedure
Measuring instrument