4
Pin No.
Pin Name
Signal Name
I/O
Purpose/Description
Normal Operation
Level
51
P47/KEY7
NF_MUTE
O
Muting of N-F when N-F is selected [H: Muting. L: Normal]
H (a)
52
P50/WE
AUDIO1
O
LINE OUT switching [H: FRONT. L: REAR]
H (a)
53
P51/RE
DSP_CONT
O
DSP ON/OFF control [L: DSP OFF (bypass). H: DSP ON]
H (a)
54
P52/CS
MUTE
O
AUDIO_MUTE output [H: Muting ON. L: Muting OFF]
H (a)
55
P53/A16
P_ON
O
Internal power control [H: ON. L: OFF]
H (a)
56
P54/A17
P_CON
O
External power control [H: ON. L: OFF]
H (a)
57
P60/A0
EVOL_DATA
I/O
DATA input/output from/to E_VOL (TDA7400)
H/L
58
P61/A1
EVOL_CLK
O
CLK output to E_VOL (TDA7400)
H/L
59
P62/A2
CD_SW1
I
Input from CDSW1 (Loading start SW)
L (a)
60
P63/A3
CD_SW2
I
Input from CDSW2 (12 cm disc detection SW)
L (a)
61
P64/A4
CD_SW3
I
Input from CDSW3 (Down & limit SW)
L (a)
62
P65/A5
CD_LO/EJ
I/O
CD mechanism loading motor control (LO/EJ) [H: Load. L: Eject]
H (a)
63
P66/A6
CD_LMON
O
CD mechanism loading motor control (ON/OFF) [H: Stop. L: Operate]
H (a)
64
P67/A7
C_F/R
O
Head switching control [H: Reverse. L: Forward]
H/L
65
P70/A8
CD_MSTOP
O
CD mechanism emergency stop output
L (a)
66
P71/A9
CD_MRST
O
CD mechanism reset output
L (a)
67
P72/A10
CD_MUTE
I
Muting input from CD mechanism
L (a)
68
P73/A11
P_ANT
O
POWER_ANT control [H: Radio mode. L: Other mode]
H (a)
69
P74/A12
PLL_CE
O
CE selection to LC72135M
H (a)
70
P75/A13
PLL_DO
O
DATA output to LC72135M
H/L
71
P76/A14
PLL_CLK
O
CLK output to LC72135M
H/L
72
P77/A15
PLL_CI
I
DATA input from LC72135M
H/L
73
P87/LED7/D7
SW40
O
VFD_Vdd2 control [H: Vdd2 ON. L: Vdd2 OFF]
H (a)
74
P86/LED6/D6
ILL_CON
O
Button illumination control [H: Illumination ON. L: Illumination OFF]
H (a)
75
P85/LED5/D5
PWIC_STBY
O
Power IC standby control [H: AMP ON. L: AMP OFF]
H (a)
76
P84/LED4/D4
PN_MC_REQ
O
Send request output to PNL_
µCOM
H (a)
77
P83/LED3/D3
PN_SC_CON
O
Operation control output to PNL_
µCOM
H (a)
78
P83/LED2/D2
PN_MC_DATA
O
DATA output to PNL_
µCOM
H/L
79
P81/LED1/D1
PN_SC_DATA
I
DATA input from PNL_
µCOM
H/L
80
P80/LED0/D0
PN_MC_CLK
O
CLK output to PNL_
µCOM
H/L
Level: High level (active)
H (a), Low level (active) L (a)
Panel Microcomputer MN101C10AAK (IC900: Combination PWB Unit)
Pin No.
Pin Name
Signal Name
I/O
Purpose/Description
Normal Operation
Level
1~5
NC (GND)
I
Not used (GND)
L
6
VREF+
VREF+
I
A/D conver ter reference voltage input terminal
7
VDD
VDD
Positive power supply terminal
8
OSC2
OSC2
Main clock connection (8.38 MHz)
9
OSC1
OSC1
Main clock connection (8.38 MHz)
10
VSS
VSS
Connected to GND
11
XI
XI
I
Connected to GND
L
12
XO
XO
O
Not used (Open)
13
MMOD
MMOD
I
Connected to GND
L
14
P00/SBO0/TXD
PN_SC_DATA
O
System control communication, data output terminal
H/L
15
P01/SBI0/RXD
PN_MC_DATA
I
System control communication, data input terminal
H/L
16
P02/SBT0
PN_MC_CLK
I
System control communication, clock input terminal
H/L
17
P03/SBO1
VFD_DATA
O
VFD driver data output
H/L
18
P04/SBI1
NC
O
Not used (Open)
L
19
P05/SBT1
VFD_CLK
O
VFD driver clock output
H/L
MICROCOMPUTER'S TERMINAL DESCRIPTION
DPX-4010,4010/PH4